Presentation
Poster 99: Eithne: A Framework for Benchmarking Micro-Core Accelerators
SessionResearch Posters Display
Event Type
Posters
Research Posters
TP
EX
EXH
TimeThursday, 21 November 20198:30am - 5pm
LocationE Concourse
DescriptionRunning existing HPC benchmarks as-is on micro-core architectures is at best difficult and most often impossible as they have a number of architectural features that makes them significantly different from traditional CPUs : tiny amounts on-chip RAM (c. 32KB), low-level knowledge specific to each device (including the host / device communications interface), limited communications bandwidth and complex or no device debugging environment. In order to compare and contrast different the micro-core architectures, a benchmark framework is required to abstract much of this complexity.
The modular Eithne framework supports the comparison of a number of micro-core architectures. The framework separates the actual benchmark from the details of how this is executed on the different technologies. The framework was evaluated by running the LINPACK benchmark on the Adapteva Epiphany, PicoRV32 and VectorBlox Orca RISC-V soft-cores, NXP RV32M1, ARM Cortex-A9, and Xilinx MicroBlaze soft-core, and comparing resulting performance and power consumption.
The modular Eithne framework supports the comparison of a number of micro-core architectures. The framework separates the actual benchmark from the details of how this is executed on the different technologies. The framework was evaluated by running the LINPACK benchmark on the Adapteva Epiphany, PicoRV32 and VectorBlox Orca RISC-V soft-cores, NXP RV32M1, ARM Cortex-A9, and Xilinx MicroBlaze soft-core, and comparing resulting performance and power consumption.
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