Presentation
Application Porting and Optimization on GPU-Accelerated POWER Architectures
Presenters
Event Type
Tutorial
TUT
Compiler Analysis and Optimization
Heterogeneous Systems
Performance
Tools
TimeMonday, 18 November 20198:30am - 5pm
Location404
DescriptionThe POWER processor has re-emerged as a technology for supercomputer architectures. One major reason is the tight integration of processor and GPU accelerator through the NVLink technology. Two major sites in the US, ORNL and LLNL, deployed their pre-exascale systems based on this new architecture (Summit and Sierra, respectively).
This tutorial will give an opportunity to obtain in-depth knowledge and experience with GPU-accelerated POWER nodes. It focuses on porting applications to a single node and covers the topics architecture, compilers, performance analysis and tuning, and multi-GPU programming. The tutorial will include an overview of the NVLink-based node architectures, lectures on first-hand experience in porting to this architecture, and exercises using tools to focus on performance.
This tutorial will give an opportunity to obtain in-depth knowledge and experience with GPU-accelerated POWER nodes. It focuses on porting applications to a single node and covers the topics architecture, compilers, performance analysis and tuning, and multi-GPU programming. The tutorial will include an overview of the NVLink-based node architectures, lectures on first-hand experience in porting to this architecture, and exercises using tools to focus on performance.
