Presentation
Accelerating Large Garbled Circuits on an FPGA-Enabled Cloud
Event Type
Workshop
W
Accelerators
Compilers
FPGA
Quantum Computing
Reconfigurable Computing
TimeSunday, 17 November 201912:10pm - 12:30pm
Location607
DescriptionGarbled Circuits (GC) is a technique for ensuring the privacy of inputs from users and is particularly well suited for FPGA implementations in the cloud where data analytics is frequently run. Secure Function Evaluation, such as that enabled by GC, is orders of magnitude slower than processing in the clear. We present our best implementation of GC on Amazon Web Services (AWS) that implements garbling on Amazon’s FPGA enabled F1 instances. In this paper we present the largest problems garbled to date on FPGA instances, which includes problems that are represented by over four million gates. Our implementation speeds up garbling 20 times over software over a range of different circuit sizes.
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