Presenter

Josef Weidendorfer is lecturer at Technische Universität München (TUM) for Computer Science. He works at the Leibniz Computing Centre (LRZ) as senior HPC scientist, working on smooth migration strategies for future HPC systems and doing research in system level and performance analysis tools, as well as parallel programming models. Before, he was senior researcher and teaching assistant at TUM. Josef did his habilitation at TUM in 2016 on simulation-driven performance analysis for parallel code, especially looking at capturing bottlenecks in the memory hierarchy of modern architectures and presenting them in a way to hint at adequate performance optimizations. He received his Ph.D. from TUM in 2003 for studying load balancing issues in car crash simulation on industrial code at BMW AG.