Presenter

Johannes is a PhD student at the Scalable Parallel Computing Group at ETH Zurich under the supervision of Prof. Torsten Hoefler, where he conducts research in high-performance computing on reconfigurable hardware. With more than three years experience in high-level synthesis tools, Johannes has accumulated a deep understanding of their strengths, weakness, and quirks, in particular in the context of massively parallel designs targeting HPC applications. He has interned with the research labs at Xilinx in Dublin and Microsoft Research Redmond, and continues to work with industry engineers on moving FPGAs into the HPC domain. As a result, he has devised and demonstrated techniques to reach peak performance on large FPGA chips, including for problems that are traditionally memory bound on CPU and GPU. In addition, Johannes is interested in new abstractions and programming models to guide and/or automate the development of cross-platform programs for HPC, and new hardware architectures.