Authors: Martin Herbordt (Boston University), Taisuke Boku (University of Tsukuba), Franck Cappello (Argonne National Laboratory), Naoya Maruyama (Lawrence Livermore National Laboratory), Andrew Putnam (Microsoft Corporation), Kentaro Sano (RIKEN), Jeffrey Vetter (Oak Ridge National Laboratory), Kazutomo Yoshii (Argonne National Laboratory), Xavier Martorell (Barcelona Supercomputing Center), Venkata Krishnan (Intel Corporation), Christian Plessl (Paderborn University), Torsten Hoefler (ETH Zurich)
Abstract: FPGA-Centric Clusters (FCCs) co-locate computation and communication to potentially yield unmatched scalability for HPC applications. FCCs have made inroads in certain domains—cloud, finance, bioinformatics, oil & gas, etc.—and are the object of much academic research with more than a dozen major efforts under way. However, nearly all aspects of building FCC systems are still ad hoc. In this BoF, leading researchers from industry, government, and academia will present the state-of-the-art in applications, architecture, programming productivity, and communication targeting FCCs. Discussion will aim at determining best practices and creating a roadmap towards future FCC-enable supercomputing. Audience participation is highly encouraged.
Long Description: In the past four years, FPGAs have gone from niche components to a central part of many data centers worldwide. But while use cases often match those of traditional accelerators (e.g., AWS), most of these millions of newly deployed FPGAs are in other configurations such as smart NICs and storage architectures. Even more critical for HPC—and for exploiting the place of FPGAs therein—is that while methods of using FPGAs as simple accelerators are converging, those for building FPGA-Centric Clusters (FCCs) are still in the era of niche-use and research. This is in spite of the fact that FPGAs support features such as HBM, PCIe, DDR, high-performant processor cores and thus can function autonomously as first-class citizens on the network. FCCs can build upon this rich set of features. It is with FCCs that FPGAs can contribute a unique capability: the co-location of compute and communication to (potentially) yield unmatched scalability. The aim of this BOF is to create a roadmap for commoditizing FCCs.
Now is the perfect time to discuss the transition path to incorporate the power of reconfigurable architectures into future heterogeneous HPC systems, concentrating on systems where the FPGAs are the central components. We use as our starting point our current understanding the characteristics of FPGAs in the context of HPC (as discussed, e.g., in last year’s BOF). We continue with experts giving status and projections in foundational technologies for turning FCCs from ad-hoc systems to productive systems for science and engineering, such as:
- Projected Workloads (simulation, data, learning, classic HPC);
- Node Architecture (CGRA, coherence, compute accelerator, network accelerator, storage accelerator);
- Programming Productivity (languages, models, environments); and
- Communication models and support (MPI-like message passing, RDMA/Libfabric-like one sided communication, point-to-point streaming connections).
This will be followed by a summary tying together the central issues. The second half of the BOF will be a general discussion driven by the interests of the attendees, potentially including topics not listed above. The goal is to identify best practices that could become the basis for standards.
This BOF is a confluence of two related sets of previous events. The first is a series of five international workshops on FPGAs for HPC. The other is the series of nine FPGA BOFs at Supercomputing held from 2010 to 2018. Starting last year, the organizers decided that, with the advent of widespread use of FPGAs in HPC, the FPGA BOF should become more targeted. Last year’s very successful edition reviewed benchmarking FPGA systems; this year we propose to explore FCCs.
This BOF is complementary to other FPGA events at SC--the H2RC workshop and a Panel—in that it focuses on systems and standards rather than research or use cases.
All session leaders have strong experience in HPC, reconfigurable computing, or both. We will select several speakers from session leaders and leading experts in academia, government, and industry.
Audience participation is a key success metric of this BOF, and half the time has been allocated for discussion.
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