The Impact of a High Performance 2D NoC on Next-Generation FPGAs
TimeWednesday, 20 November 20193:30pm - 4pm
DescriptionWith accelerators being used to boost high-performance computing, FPGAs are increasingly popular options offering a reconfigurable datapath. Traditional FPGA architectures connect the external interfaces to the periphery beachfront of the FPGA fabric. But as FPGA compute capacity and external interface bandwidth continue to grow exponentially, the frequency for the FPGA logic and interconnect does not scale, leading to a mismatch in connecting the FPGA fabric to the outside world. An innovative Network-on-Chip (NoC) architecture, with a bi-sectional bandwidth of 20Tbps, addresses this issue. It allows external interface controllers to connect to each other, and gracefully moves data in, out, and around the FPGA fabric. The NoC overlays a 2D network of high-speed packet-based communication infrastructure providing 160 access points connecting into the FPGA fabric. Learn how 2D NoC improves performance and eases design by reducing routing congestion, eliminating floor-planning challenges, and decoupling clock domains.