The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Authors: Jeff Young (Georgia Institute of Technology), Jiajia Li (Pacific Northwest National Laboratory (PNNL)), Kevin Barker (Pacific Northwest National Laboratory (PNNL)), Mark Klein (Swiss National Supercomputing Centre (CSCS)), Alice Koniges (University of Hawaii), James Laros (Sandia National Laboratories), Jeffrey Vetter (Oak Ridge National Laboratory)
Abstract: The recent explosion in architectural diversity in the supercomputing community is supported by the use of user-focused testbeds that allow researchers to test their applications on hardware that may be hard to access at smaller scales. This BoF will bring together panelists from advanced architecture testbed efforts including CSCS’s User lab, PNNL’s CENATE testbed, HAAPS at SNL, the Rogues Gallery at Georgia Tech, ExCL at ORNL, and the Maui HPC Center to discuss increasingly diverse architectures and challenges for using them. Panelists and attendees will debate topics to better meet the growing demand for access to novel architecture systems.
Long Description: The supercomputing community is in the midst of a period of unprecedented architectural innovation. The explosion in architectural diversity leads to a number of challenges, including understanding the potential performance impact of new architectural technologies on workloads of interest and guidance for architectural design from application and algorithm features. To address these challenges, a number of architectural testbed efforts have been established, including CENATE at Pacific Northwest National Laboratory, HAAPS at Sandia National Laboratory, Rogues Gallery at Georgia Tech, the User lab at CSCS, HPCMP at several testbed sites, and ExCL at Oak Ridge National Laboratory. This BoF brings together researchers and practitioners involved in these and other efforts to ensure alignment of efforts, increased coverage of diverse architectures, sharing of lessons learned in advanced architectural exploration, and support for efforts to establish and use common proxy applications and benchmarks. The audience are encouraged to be actively involved in discussion with topics ranging from applications, algorithm design, programming language, compiler, resilience, security aspects.
Our BoF aims to cover a number of topics: architectural diversity, proxy applications and benchmarks, and hardware/software co-design. Foremost among them is the dimension of architectural diversity in processors, memory, and network that results as architectural designers grapple with increased demands on performance and energy efficiency. In the processing space, compute elements such as multi-core CPUs, GPUs, FPGAs, and advanced accelerators such as Tensor Processing Units (TPUs) and Emu are increasingly finding their way into HPC system installations. Similarly, memory technologies including conventional DRAM, stacked memory (e.g., HBM), and non-volatile and storage-class memory are leading to increased heterogeneity and are placing additional burdens on applications seeking to make the most effective use of limited memory resources. In the interconnection network space, electrical packet-switched networks, optical circuit-switched networks, and advanced NIC and switch designs are leading to new network topologies and performance characteristics that are having an impact on application communication behavior. BoF panelists will have an opportunity to describe the testbed systems that are currently in place, and all attendees will have a chance to discuss current gaps in testbed installations.
The BoF will also provide the opportunity for practitioners to identify currently used proxy applications and benchmarks as well as the current gaps that need to be addressed with additional software development. This BoF will provide a venue for discussing what constitutes a realistic proxy application or what benchmarks would help improve the utility of advanced architecture testbeds.
Hardware/software co-design efforts for new architectures and technologies are supported by architectural modeling and simulation tools, but the development of software stacks to support novel architectural technologies requires the availability of early-access testbed systems. Key challenges in this area include the need to work with immature software stacks, as well as non-disclosure agreements that must be in place to support early access to pre-production hardware. This BoF will provide an opportunity for participants to share lessons learned in these areas.
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