Supervisor: Xiaoyi Lu (Ohio State University)
Abstract: Erasure Coding (EC) NIC offload is a promising technology for designing next-generation distributed storage systems. To alleviate the EC overhead, various hardware-based Erasure Coding schemes have been proposed to leverage the advanced compute capabilities on modern HPC clusters. However, this poster has identified some critical limitations of current-generation EC NIC offload schemes on modern SmartNICs and the missing of exploiting heterogeneous hardware available on modern HPC clusters in parallel. To address these limitations, this poster first proposes a unified benchmark suite to benchmark, measure and characterize hardware-optimized erasure coders. Then, it proposes a Multi-Rail EC concept which enables upper-layer applications to leverage heterogeneous hardware to perform EC operations simultaneously. Finally, it proposes a new EC NIC offload paradigm based on the tripartite graph model, namely TriEC. TriEC supports both encode-and-send and receive-and-decode offload primitives efficiently.
ACM-SRC Semi-Finalist: no
Poster Summary: PDF
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