Workshop
:
Data Flow Pipes: A SYCL Extension for Spatial Architectures
Event Type
Workshop
Registration Categories
W
Tags
Accelerators
Compilers
FPGA
Quantum Computing
Reconfigurable Computing
TimeSunday, 17 November 201911am - 11:15am
Location607
DescriptionFIFOs are a common construct in design for spatial and data flow architectures. OpenCL 2.0 defined a “pipe” feature to expose the FIFO construct, but the design didn’t meet all needs of spatial architectures. This talk describes a pipes extension to the Khronos SYCL single-source, C++-based programming framework, that exposes a pipe abstraction which closes the gaps in the OpenCL design, while also offering a more usable interface. The C++ type system is leveraged to provide static connectivity guarantees without extensive compiler implementation effort, and to provide well-defined interaction with C++ features. The described extension provides a usable interface that can also act as a substrate for additional abstractions to be built on top. This talk will motivate the utility of FIFOs/pipes in high level language FPGA design, describe the SYCL pipes extension and its mapping to SPIR-V and OpenCL, and provide examples of use in common spatial design patterns.
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