2nd International Workshop on Performance, Portability, and Productivity in HPC (P3HPC)
Event Type
Registration Categories
Parallel Programming Languages, Libraries, and Models
TimeFriday, 22 November 20198:30am - 8:31am
DescriptionThe ability for applications to achieve both portability and high performance across computer architectures remains an open challenge. It is often unrealistic or undesirable for developers to maintain separate implementations for each target architecture, yet in many cases, achieving high performance and fully utilizing an architecture’s underlying features requires the use of specialized language constructs and libraries. Likewise, abstractions and standards that promise portability cannot necessarily deliver high performance without additional algorithmic considerations, and performance compromises are often made to remain portable. Application developers, who strive to work productively while balancing these concerns, often find the goal to be elusive.

There is a clear need to develop ways of managing the complexity that arises from system diversity that balance the need for performant specializations with the economy of appropriate and efficient abstractions. Despite growth in the number of available architectures, there are similarities that represent general trends in current and emerging HPC hardware: increased thread parallelism; wider vector units; specialized hardware units; and deep, complex, memory hierarchies. This in turn offers some hope for common programming techniques and language support as community experience matures.

The purpose of this workshop is to provide an opportunity for attendees to share ideas, practical experiences, and methodologies for tackling the challenge of achieving performance portability and developer productivity across current and future homogeneous and heterogeneous computer architectures.
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